1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a delay locked loop circuit.
2. Description of the Background Art
In recent years, as semiconductor memory devices operate with higher speed, some dynamic random access memories (DRAMs) such as a Direct Rambus DRAM (D-RDRAM) (R) or a double data rate synchronous DRAM (DDR SDRAM) have a delay locked loop (DLL) circuit mounted therein to realize high-speed operation.
However, with the DLL mounted, consumption current is disadvantageously increased. Some products such as portable terminals, e.g. notebook-sized personal computers or PDAs (Personal Digital Assistants) strongly require low power consumption. Thus, it has been a challenge to reduce power consumption in a semiconductor memory device.
An object of the present invention is to provide a semiconductor memory device having reduced power consumption while it operates at a high speed.
According to one aspect of the present invention, a semiconductor memory device includes a memory array, a first output circuit, a DLL circuit, and a control circuit.
The memory array includes memory cells arranged in a matrix of rows and columns. The first output circuit outputs a first output signal to outside the semiconductor memory device in synchronization with a first clock signal, in response to data reading from the memory array. The DLL circuit receives and delays an external clock signal, and generates the first clock signal. The control circuit makes the DLL circuit activate the first clock signal in accordance with a control signal from outside the semiconductor memory device.
According to another aspect of the present invention, a semiconductor memory device includes a memory array, a data output circuit and a DLL circuit.
The memory array includes memory cells arranged in a matrix of rows and columns. The data output circuit receives read data from the memory array and outputs the received data to outside the semiconductor memory device in synchronization with an internal clock signal. The DLL circuit receives and delays an external clock signal, and generates the internal clock signal.
The DLL circuit includes a delay line receiving the external clock signal and delaying the received signal for delay time according to a delay control signal, a phase detector detecting a phase difference between an output of the delay line and the external clock signal, a delay control circuit outputting the delay control signal in accordance with an output of the phase detector, and a clock driving circuit activated in accordance with the output of the phase detector and receiving the output of the delay line to output the internal clock signal.
Therefore, a main advantage of the present invention is that the output of the DLL circuit is driven as required, so that power consumption can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.